A memory system may include a plurality of memory cells having a common data input. Each memory cell may include first and second storage nodes, a first pass transistor to write a logic state from the common data input to the first storage node, and a second pass transistor to write an opposite sense of the logic state to the second storage node. Each memory cell may include first and second inverters opposingly coupled between the first and second storage nodes to maintain opposite-sense logic states at the first and second storage nodes.
When a logic state is written to the first or second storage node, over an opposite-sense of the logic state, a write-contention in one or both of the inverters may delay completion of the write operation. Write contention may be overcome by using larger pass transistors, which may consume more area and power.
In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.